The present invention relates to integrated circuits which require capacitors.
It is difficult to realize large capacitances in an integrated circuit. Typical MOS capacitors may have a specific capacitance which requires a number of square microns to provide even one picoFarad of capacitance. (Capacitance is directly proportional to the area of semiconducting substrate which may be used for integrating a capacitor.) However, many functional circuits require the use of relatively high capacitances, which cannot practicably be implemented as a physical integrated circuit capacitor. (For example, this may be particularly difficult when it is necessary to implement filters with cutoff frequencies in the audio band or below, e.g. 10 Hz.)
The problem may be resolved by the use of a so-called capacitance multiplier circuit. Several circuits which implement the function of a capacitance multiplier for a real (physical) capacitor (having an easily integratable size) and which are described in literature. These circuits often contain an operational amplifier.
A typical capacitance multiplier circuit which may be easily integrated is shown in FIG. 1. The intermediate node between the two resistances R1 and R2 constitutes the terminal of a "virtual" capacitor having a capacitance given by: EQU Cm=R1/R2 C
where C is the capacitance of a physically integrated capacitor.
In order to obtain a virtual capacitance of about 10 nF from a physical capacitance of about 100 pF, it is necessary to use two well matched integrated resistances having a ratio of resistance equal to about 100. Moreover, the smaller resistance (R2) should advantageously have a relatively small value because it determines the series resistance of the virtual capacitance which is obtained.
The realization of a pair of well matched integrated resistances which have a relatively large resistance ratio and which have low to moderate temperature coefficients is not a technically insurmountable problem, but the solution requires a large amount of surface area on a semiconductor substrate.
An alternative and more advantageous solution is provided by the present invention. One main object of the invention is to provide an improved capacitance multiplier circuit which utilizes two field effect transistors in place of the two resistances connected in series as shown in FIG. 1.
In the circuit of the invention, a given resistance ratio is functionally implemented by using the ratio between the ON-resistances (e.g. channel resistances) of the two field effect transistors. These transistors have dimensions, commonly indicated in terms of channel width (W) and channel length (L) as a ratio W/L, which is selected to obtain the desired ratio between the respective ON-resistances. The two field effect transistors are essentially used in a state of conduction, by suitably biasing a control gate of a latch transistor.
The advantages of the capacitance multiplier circuit of the invention are remarkable. It offers greater versatility of the circuit in comparison to known circuits using two integrated resistances. In many cases, the circuit of the invention as intended permits the saving of semiconductor area.
According to a preferred embodiment of the invention, the two field effect transistors each having a source region and a drain region separated by a channel region topped by a control gate structure are controlled by an applied biasing voltage. This permits implementation of an RC circuit utilizing an integrated resistance (R) and a capacitance (C). The virtual capacitance is produced by means of the multiplier circuit of the invention, which is intrinsically temperature-compensated. This is possible because the biasing voltage which is applied to the control gate of any one of the two transistors may be varied independently from the biasing voltage which is applied to the other transistor.
According to such a preferred embodiment, the capacitance multiplier circuit of the invention is provided with a biasing circuit having at least two output nodes which are connected to the control gate of the two field effect transistors. Each of the voltages which are produced on the output nodes of the biasing circuit may be generated according to a certain temperature-dependency law, for varying the ratio between the channel resistances of the two field effect transistors as a function of the temperature. This is done in order to compensate for the variation resistance caused by a variation of temperature.
In this way, a temperature independent integrated RC circuit may be implemented by using a capacitor having a multiplied virtual value.
Of course, for applications where such a temperature compensation is not necessary or required, the two field effect transistors may be biased with fixed voltages.